1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device for reducing a film thickness of a gate oxide film to relax an electric field in a drain region.
2. Description of the Related Art
In conventional methods of manufacturing a semiconductor device, for example, the following technique is known. A gate oxide film is formed on a P type silicon substrate. A gate electrode formed of polysilicon is formed on the gate oxide film. Then, arsenic ions are implanted into the substrate using the gate electrode by a self-alignment technique to form a low concentration diffusion layer with an LDD (Lightly Doped Drain) structure. Thereafter, a side wall spacer is formed on a side surface of the gate electrode to form a high concentration diffusion layer with an LDD structure. This manufacturing method forms a semiconductor device including a gate oxide film with high insulation properties and reliability. This technology is described for instance in Japanese Patent Application Publication No. Hei 11(1999)-2890088.
In conventional methods of manufacturing a semiconductor device, for example, the following technique is known. A gate oxide film is formed on a semiconductor layer to deposit a polysilicon film on the gate oxide film. Then, the polysilicon film is selectively removed to form a gate electrode on the gate oxide film. Next, the gate oxide film is selectively removed by etching using the gate electrode as a mask. At this time, an etchant penetrates into a lower side of an end portion of the gate electrode to remove the gate oxide film. Then, a thermal oxidization is carried out to form an oxide film on an exposed portion of the semiconductor layer. Thereafter, a source region with a DDD (Double Diffusion Drain) structure and a drain region are formed by a self-aligning technique using the gate electrode. This manufacturing method forms a semiconductor device that realizes an electric field relaxation in the drain region. This technology is described for instance in Japanese Patent Application Publication No. 2001-250941.
In conventional methods of manufacturing a semiconductor device, for example, the following technique is known. A sacrificial oxide film of about 100 nm is first formed on the upper surface of the substrate in forming a high voltage circuit and a low voltage circuit on the same substrate. In a region where the high voltage circuit is formed, impurity ions are implanted into an upper surface of the sacrificial oxide film at an acceleration voltage of about 150 keV. Then, a well region is formed in a region where a PMOS transistor of the high voltage circuit or the like is formed. After that, the sacrificial oxide film is removed and a first gate oxide film of about 13 nm is formed on an upper surface of a substrate of a region where both circuits are formed. Next, a well region is formed in a region where a PMOS transistor of the low voltage circuit is formed. After that, a second gate oxide film of about 8 nm is formed on the upper surface of the substrate of the region where both circuits are formed, so that PMOS transistors of both circuits are formed. This technology is described for instance in Japanese Patent Application Publication No. 2004-104141.
As explained above, in the conventional method of manufacturing a semiconductor device, the drain region is formed to have the LDD structure, thereby realizing the electric field relaxation in the drain region. For this reason, first, the low concentration drain region, which makes the drain region, is formed by the self-alignment technique using the gate electrode. Next, the side wall spacer is formed on the side surface of the gate electrode. Then, the high concentration drain region is formed by the self-alignment technique using the side wall spacer. However, in this manufacturing method, a process for forming the side wall spacer is needed to form the LDD structure. This causes a problem in which the number of masks and that of manufacturing processes are increased to require a high manufacturing cost. Moreover, there is a problem in which the manufacturing process becomes complicated.
Moreover, in the conventional method of manufacturing a semiconductor device, when the drain region is formed to have the DDD structure, the gate oxide film, which is positioned between the gate electrode and the drain region, is thickly formed. In this manufacturing method, after the gate oxide film and the gate electrode are formed on the semiconductor layer, the gate oxide film is removed by etching using the gate electrode as a mask. After that, a thermal oxidation process is needed to increase the film thickness of the gate oxide film between the gate electrode and the drain electrode. However, this manufacturing method causes a problem in which the number of manufacturing processes is increased, resulting in an increase in manufacturing cost. Moreover, there is a problem in which the manufacturing process becomes complicated.
Moreover, in the conventional method of manufacturing a semiconductor device, in order to form a CMOS transistor on the same substrate, an N type well region is formed and thereafter a P type well region is formed in the N type well region. Then, in both well regions, impurity ions are implanted into a channel region to adjust an impurity concentration of a surface region of the semiconductor layer for the purpose of suppressing a short channel effect. Thereafter, a source region and a drain region are formed in both well regions, respectively. However, in this manufacturing method, the impurity concentration of the region where the drain region is formed is relatively high, so that the drain region is less likely to be widely diffused in the channel direction and the depth direction. This increases an electron current density in the drain region, resulting in a structure in which a parasitic NPN transistor is easily turned on. Then, there is a problem in which a withstand voltage characteristic deteriorates when the semiconductor device is turned on.